integrated device technology, inc. description: the fct16841at/bt/ct/et and fct162841at/bt/ct/ et 20-bit transparent d-type latches are built using advanced dual metal cmos technology. these high-speed, low-power latches are ideal for temporary storage of data. they can be used for implementing memory address latches, i/o ports, and bus drivers. the output enable and latch enable controls are organized to operate each device as two 10-bit latches or one 20-bit latch. flow-through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. the fct16841at/bt/ct/et are ideally suited for driving high-capacitance loads and low-impedance backplanes. the output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. the fct162841at/bt/ct/et have balanced output drive with current limiting resistors. this offers low ground bounce, minimal undershoot, and controlled output fall times?educing the need for external series terminating resistors. the fct162841at/bt/ct/et are plug-in replacements for the fct16841at/bt/ct/et and abt16841 for on-board inter- face applications. the idt logo is a registered trademark of integrated device technology, inc. fast cmos 20-bit transparent latches idt54/74fct16841at/bt/ct/et idt54/74fct162841at/bt/ct/et functional block diagram 2 q 1 2 oe 2 le 2 d 1 2556 drw 02 to 9 other channels c d 1 oe 1 le 1 q 1 1 d 1 2556 drw 01 to 9 other channels c d military and commercial temperature ranges july 1996 1996 integrated device technology, inc. 5.18 dsc-2556/7 1 features: common features: 0.5 micron cmos technology high-speed, low-power cmos replacement for abt functions typical t sk (o) (output skew) < 250ps low input and output leakage 1 m a (max.) esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) packages include 25 mil pitch ssop, 19.6 mil pitch tssop, 15.7 mil pitch tvsop and 25 mil pitch cerpack extended commercial range of -40 c to +85 c ? cc = 5v 10% features for fct16841at/bt/ct/et: high drive outputs (-32ma i oh , 64ma i ol ) power off disable outputs permit ?ive insertion typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25 c features for fct162841at/bt/ct/et: balanced output drivers: 24ma (commercial), 16ma (military) reduced system switching noise typical v olp (output ground bounce) < 0.6v at v cc = 5v,t a = 25 c
5.18 2 idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges pin configurations 1 q 1 gnd 1 q 3 v cc 1 oe gnd 1 q 10 gnd v cc 1 q 2 1 q 4 1 q 5 1 q 6 1 q 7 1 q 8 1 q 9 2 q 1 2 q 2 2 q 3 2 q 5 2 q 6 2 q 4 1 le 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v cc 1 d 5 1 d 6 1 d 7 1 d 8 1 d 9 1 d 10 2 d 2 gnd gnd 47 37 38 39 40 41 42 43 44 45 46 33 34 35 36 56 55 49 50 51 52 53 54 48 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 2556 drw 04 cerpack top view e56-1 gnd 2 q 7 2 q 8 2 oe 25 26 27 28 2 d 4 v cc 2 d 5 2 d 6 gnd 2 d 7 2 d 8 2 d 9 2 d 10 2 le 29 30 31 32 2 q 9 2 q 10 2 d 1 2 d 3 1 q 1 gnd 1 q 3 v cc 1 oe gnd 1 q 10 gnd 1 q 2 1 q 4 1 q 5 1 q 6 1 q 7 1 q 8 1 q 9 2 q 3 v cc gnd 2 q 4 2 q 5 2 q 7 2 q 8 2 q 6 2 oe 1 le 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v cc 1 d 5 1 d 6 1 d 7 1 d 8 1 d 9 1 d 10 gnd gnd 2556 drw 03 47 37 38 39 40 41 42 43 44 45 46 33 34 35 36 56 55 49 50 51 52 53 54 48 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 ssop/ tssop/tvsop top view so56-1 so56-2 so56-3 2 q 1 2 q 2 2 q 10 2 q 9 2 d 3 2 d 4 v cc 2 d 5 2 d 7 2 d 8 2 d 6 gnd 2 d 9 2 d 10 2 le 29 30 31 32 25 26 27 28 2 d 1 2 d 2
idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges 5.18 3 pin description 2556 tbl 01 absolute maximum ratings (1) function table (1) capacitance (t a = +25 c, f = 1.0mhz) 2556 lnk 04 notes: 2556 tbl 02 1. h = high voltage level l = low voltage level x = don? care z = high impedance 2. output level before xle high-to-low transition. note: 1. this parameter is measured at characterization but not tested. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6.0 pf c out output capacitance v out = 0v 3.5 8.0 pf pin names description xdx data inputs xle latch enable input (active high) x oe output enable input (active low) xqx 3-state outputs inputs outputs xdx xle x oe oe xqx hh lh lhll xllq (2) xxhz symbol description max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7.0 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 v t stg storage temperature C65 to +150 c i out dc output current C60 to +120 ma notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all device terminals except fct162xxxt output and i/o terminals. 3. output and i/o terminals for fct162xxxt. 2556 lnk 03
5.18 4 idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40 c to +85 c, v cc = 5.0v 10%; military: t a = C55 c to +125 c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i i h input high current (input pins) (5) v cc = max. v i = v cc 1 m a input high current (i/o pins) (5) 1 i i l input low current (input pins) (5) v i = gnd 1 input low current (i/o pins) (5) 1 i ozh high impedance output current v cc = max. v o = 2.7v 1 m a i ozl (3-state output pins) (5) v o = 0.5v 1 v ik clamp diode voltage v cc = min., i in = C18ma C 0.7 C 1.2 v i os short circuit current v cc = max., v o = gnd (3) C80 C 140 C 225 ma v h input hysteresis 100 mv i ccl i cch i ccz quiescent power supply current v cc = max., v in = gnd or v cc 5 500 m a 2556 lnk 05 output drive characteristics for fct16841t 2556 lnk 06 output drive characteristics for fct162841t 2556 lnk 07 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25 c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. duration of the condition can not exceed one second. 5. the test limit for this parameter is 5 m a at t a = C55 c. symbol parameter test conditions (1) min. typ. (2) max. unit i odl output low current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) 60 115 200 ma i odh output high current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) C60 C115 C200 ma v oh output high voltage v cc = min. v in = v ih or v il i oh = C16ma mil. i oh = C24ma com'l. 2.4 3.3 v v ol output low voltage v cc = min. v in = v ih or v il i ol = 16ma mil. i ol = 24ma com'l. 0.3 0.55 v symbol parameter test conditions (1) min. typ. (2) max. unit i o output drive current v cc = max., v o = 2.5v (3) C50 C 180 ma v oh output high voltage v cc = min. i oh = C3ma 2.5 3.5 v v in = v ih or v il i oh = C12ma mil. i oh = C15ma com'l. 2.4 3.5 v i oh = C24ma mil. i oh = C32ma com'l. (4) 2.0 3.0 v v ol output low voltage v cc = min. v in = v ih or v il i ol = 48ma mil. i ol = 64ma com'l. 0.2 0.55 v i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v 1 m a
idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges 5.18 5 power supply characteristics 2556 tbl 08 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp n cp /2 + f i n i ) i cc = quiescent current (i ccl , i cch and i ccz ) d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at f i symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 1.5 ma i ccd dynamic power supply current (4) v cc = max. outputs open x oe = gnd one input toggling 50% duty cycle v in = v cc v in = gnd 60 100 m a/ mhz i c total power supply current (6) v cc = max. outputs open fi =10mhz v in = v cc v in = gnd 0.6 1.5 ma 50% duty cycle x oe = gnd xle = v cc one bit toggling v in = 3.4v v in = gnd 0.9 2.3 v cc = max. outputs open fi = 2.5mhz v in = v cc v in = gnd 3.0 5.5 (5) 50% duty cycle x oe = gnd xle = v cc twenty bits toggling v in = 3.4v v in = gnd 8.0 20.5 (5)
5.18 6 idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges switching characteristics over operating range 2556 tbl 09 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. 4. this limit is guaranteed but not tested. 5. this condition is guaranteed but not tested. fct16841at/162841at fct16841bt/162841bt com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay xdx to xqx c l = 50pf r l = 500 w 1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 ns (le = high) c l = 300pf (5) r l = 500 w 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 t plh t phl propagation delay xle to xqx c l = 50pf r l = 500 w 1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 ns c l = 300pf (5) r l = 500 w 1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 t pzh t pzl output enable time x oe to xqx c l = 50pf r l = 500 w 1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 ns c l = 300pf (5) r l = 500 w 1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 t phz t plz output disable time x oe to xqx c l = 5pf (5) r l = 500 w 1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 ns c l = 50pf r l = 500 w 1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 t su set-up time high or low, xdx to xle c l = 50pf r l = 500 w 2.5 2.5 2.5 2.5 ns t h hold time high or low, xdx to xle 2.5 3.0 2.5 2.5 ns t w xle pulse width high 4.0 (4) 5.0 4.0 (4) 4.0 (4) ns t sk (o) output skew (3) 0.5 0.5 0.5 0.5 ns
idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges 5.18 7 switching characteristics over operating range 2556 tbl 10 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. 4. this limit is guaranteed but not tested. 5. this condition is guaranteed but not tested. fct16841ct/162841ct fct16841et/162841et com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay xdx to xqx c l = 50pf r l = 500 w 1.5 5.5 1.5 6.3 1.5 3.4 ns (le = high) c l = 300pf (5) r l = 500 w 1.5 13.0 1.5 15.0 1.5 7.5 t plh t phl propagation delay xle to xqx c l = 50pf r l = 500 w 1.5 6.4 1.5 6.8 1.5 3.7 ns c l = 300pf (5) r l = 500 w 1.5 15.0 1.5 16.0 1.5 7.5 t pzh t pzl output enable time x oe to xqx c l = 50pf r l = 500 w 1.5 6.5 1.5 7.3 1.5 4.4 ns c l = 300pf (5) r l = 500 w 1.5 12.0 1.5 13.0 1.5 9.0 t phz t plz output disable time x oe to xqx c l = 5pf (5) r l = 500 w 1.5 5.7 1.5 6.0 1.5 3.6 ns c l = 50pf r l = 500 w 1.5 6.0 1.5 6.3 1.5 3.6 t su set-up time high or low, xdx to xle c l = 50pf r l = 500 w 2.5 2.5 1.0 ns t h hold time high or low, xdx to xle 2.5 2.5 1.0 ns t w xle pulse width high 4.0 (4) 4.0 (4) 3.0 (4) ns t sk (o) output skew (3) 0.5 0.5 0.5 ns
5.18 8 idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges test circuits and waveforms test circuits for all outputs enable and disable times propagation delay set-up, hold and release times pulse width switch position pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. test switch disable low enable low closed all other tests open open drain definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. 2556 lnk 11 notes: 1. diagram shown for input control enable-low and input control disable-high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns 2556 drw 09 2556 drw 07 2556 drw 05 2556 drw 06 2556 drw 08
idt54/74fct16841at/bt/ct/et, 162841at/bt/ct/et fast cmos 20-bit transparent latches military and commercial temperature ranges 5.18 9 ordering information idt xx temp. range xxxx device type x package x process 54 74 C55 c to +125 c C40 c to +85 c blank b pv pa pf e 16841at 16841bt 16841ct 16841et 162841at 162841bt 162841ct 162841et commercial mil-std-883, class b shrink small outline package (so56-1) thin shrink small outline package (so56-2) thin very small outline package (so56-3) cerpack (e56-1) non-inverting 20-bit transparent latch fct 2556 drw 10
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